1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device using a pre-fetch method and a semiconductor system including the same.
2. Description of the Related Art
Generally, a data input/output (I/O) of a synchronous semiconductor memory device is performed in synchronization with an internal clock signal that is generated based on an external clock signal. Examples of synchronous semiconductor memory devices include single data rate (SDR) synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, and graphic DDR5 (GDDR5) SDRAM. The devices DDR, DDR2, DDR3 SDRAM, and GDDR5 SDRAM are multi-bit pre-fetch type semiconductor memory devices. For example, an 8-bit pre-fetch scheme is used in DDR3 SDRAM and GDDR5 SDRAM. In the 8-bit pre-fetch scheme, whenever a column command is generated in a semiconductor memory device, 8-bit data are outputted to an external device in series through one data I/O pin for 4 cycles of an operation clock.
It is expected that a 16-bit pre-fetch scheme will be applied to the next-generation semiconductor memory devices, such as a Mobile DDR4 that is being developed.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device to which an 8-bit pre-fetch scheme has been applied. FIG. 2 is a block diagram illustrating a conventional semiconductor memory device to which a 16-bit pre-fetch scheme has been applied.
Referring to FIGS. 1 and 2, the conventional semiconductor memory device include a memory bank 10, an address decoder 20, a data I/O unit 30, a command decoder 40, 16 data I/O pads DQ<1:16>, a column operation region 60, and a row operation region 50, irrespective of whether an 8-bit pre-fetch scheme or a 16-bit pre-fetch scheme is applied to the conventional semiconductor memory device. The memory bank 10 includes an upper memory region 10<UP> and a lower memory region 10<DN>. The data I/O unit 30 includes an upper data I/O unit 30<UP> and a lower data I/O unit 30<DN>. The command decoder 40 includes a column command decoder (not shown) and a row command decoder (not shown). The address decoder 20 includes a column address decoder (not shown) and a row address decoder (not shown). Furthermore, in the semiconductor memory device of FIGS. 1 and 2, the row operation region 50 performs an operation for selecting a word line of the memory bank 10 in response to a row command ROW_CMD generated from the row command decoder 40 and a row address ROW_ADDR generated from the row address decoder 20. Furthermore, the column operation region 60 performs an operation for selecting a bit line of the memory bank 10 in response to a column command COL_CMD generated from the row command decoder 40 and a column address COL_ADDR generated from the row address decoder 20.
First, when utilizing the 8-bit pre-fetch scheme, the memory bank 10 and the column operation region 60 of FIG. 1 input/output 16 8-bit data DATA1<1:8>, DATA2<1:8>, DATA3<1:8>, . . . , DATA15<1:8>, and DATA16<1:8> through the respective 16 data I/O pads DQ<1:16> at the same time. That is, when the column command COL_CMD and the column address COL_ADDR are applied, the memory bank 10 and the column operation region 60 input/output 128 data DATA<1:128> in parallel. The lower memory region 10<DN> of the memory bank 10 inputs/outputs 64 data DATA<1:64> from/to a lower 8 data I/O pads DQ<1:8> of the 16 data I/O pads DQ<1:16>. Similarly, the upper memory region 10<UP> of the memory bank 10 inputs/outputs 64 data DATA<65:128> from/to an upper 8 data I/O pads DQ<9:16> of the 16 data I/O pads DQ<1:16>.
The 128 data DATA<1:128> that are inputted to or outputted from the memory bank 10 are subject to serial-to-parallel conversion by the data I/O unit 30 through 128 local lines LIO<1:128> and 128 global lines GIO<1:128> and are then inputted to or outputted from the 16 data I/O pads DQ<1:16>. That is, the 128 data DATA<1:128> that need to be outputted from the memory bank 10 to the 16 data I/O pads DQ<1:16> are transferred to the data I/O unit 30 through the 128 local lines LIO<1:128> and the 128 global lines GIO<1:128>, serialized by the data I/O unit 30 by 8 bits, and then outputted to the 16 data I/O pads DQ<1:16>. In contrast, the 128 data DATA<1:128> that need to be transferred from the 16 data I/O pads DQ<1:16> to the memory bank 10 are inputted to the 16 data I/O pads DQ<1:16> by 8 bits in series, parallelized by the data I/O unit 30, and then transmitted to the memory bank 10 through the 128 global lines GIO<1:128> and the 128 local lines LIO<1:128>.
Furthermore, the upper data I/O unit 30<UP> of the data I/O unit 30 performs serial-to-parallel or parallel-to-serial conversion on the 64 data DATA<1:64> between the upper 8 data I/O pads DQ<9:16> and the upper memory region 10<UP> and inputs/outputs the converted 64 data DATA<1:64>. Furthermore, the lower data I/O unit 30<DN> of the data I/O unit 30 performs serial-to-parallel or parallel-to-serial conversion on the 64 data DATA<65:128> between the lower 8 data I/O pads DQ<1:8> and the lower memory region 10<DN> and inputs/outputs the converted 64 data DATA<65:128>.
The command decoder 40 generates the column command COL_CMD by decoding an external command CMD and transfers the column command COL_CMD to the column operation region 60 to perform column data I/O operations.
The address decoder 20 generates the column address COL_ADDR by decoding an external address ADD and transfers the column address COL_ADDR to the column operation region 60 to select the 128 data DATA<1:128> to be used in I/O operations from the memory bank 10.
When utilizing the 16-bit pre-fetch scheme, the memory bank 10 and the column operation region 60 of FIG. 2 input/output 16 16-bit data DATA1<1:16>, DATA2<1:16>, DATA3<1:16>, . . . , DATA15<1:16>, and DATA16<1:16> through the respective 16 data I/O pads DQ<1:16>, at the same time. That is, when the column command COL_CMD and the column address COL_ADDR are applied, the memory bank 10 and the column operation region 60 input/output 256 data DATA<1:256> in parallel. The lower memory region 10<DN> of the memory bank 10 inputs/outputs the 128 data DATA<1:128> from/to a lower 8 data I/O pads DQ<1:8> of the 16 data I/O pads DQ<1:16>. Similarly, the upper memory region 10<UP> of the memory bank 10 inputs/outputs the 128 data DATA<129:256> from/to an upper 8 data I/O pads DQ<9:16> of the 16 data I/O pads DQ<1:16>.
The 256 data DATA<1:256> inputted to or outputted from the memory bank 10 are subject to serial-to-parallel conversion by the data I/O unit 30 through 256 local lines LIO<1:256> and 256 global lines GIO<1:256> and are inputted to or outputted from the 16 data I/O pads DQ<1:16>. That is, the 256 data DATA<1:256> to be outputted from the memory bank 10 to the 16 data I/O pads DQ<1:16> are transferred to the data I/O unit 30 through the 256 local lines LIO<1:256> and the 256 global lines GIO<1:256>, serialized by the data I/O unit 30 by 16 bits, and then outputted to the 16 data I/O pads DQ<1:16>. In contrast, the 256 data DATA<1:256> to be transferred from the 16 data I/O pads DQ<1:16> to the memory bank 10 are inputted to the 16 data I/O pads DQ<1:16> by 16 bits in series, parallelized by the data I/O unit 30, and then transmitted to the memory bank 10 through the 256 global lines GIO<1:256> and the 256 local lines LIO<1:256>.
Furthermore, the upper data I/O unit 30<UP> of the data I/O unit 30 performs serial-to-parallel or parallel-to-serial conversion on the 128 data DATA<1:128> between the upper 8 data I/O pads DQ<9:16> and the upper memory region 10<UP> and inputs/outputs the converted 128 data DATA<1:128>. The lower data I/O unit 30<DN> of the data I/O unit 30 performs serial-to-parallel or parallel-to-serial conversion on the 128 data DATA<129:256> between the lower 8 data I/O pads DQ<1:8> and the lower memory region 10<DN> and inputs/outputs the converted 128 data DATA<129:256>.
The command decoder 40 generates the column command COL_CMD by decoding an external command CMD and transfers the generated column command COL_CMD to the column operation region 60 to perform column data I/O operations.
The address decoder 20 generates the column address COL_ADDR by decoding an external address ADD and transfers the generated column address COL_ADDR to the column operation region 60 to select the 256 data DATA<1:256> to be used in I/O operations from the memory bank 10.
As described above, when applying the 16-bit pre-fetch scheme to the semiconductor memory device of FIG. 2, the total of the 256 local lines LIO<1:256> and the 256 global lines GIO<1:256> are necessary since the 16 data DATA1<1:16>, DATA2<1:16>, DATA3<1:16>, . . . , DATA15<1:16>, and DATA16<1:16> are outputted through the respective 16 data I/O pads DQ<1:16>. However, when applying the 8-bit pre-fetch scheme to the semiconductor memory device of FIG. 1, only the total of the 128 local lines LIO<1:128> and the 128 global lines GIO<1:128> are necessary because the 8 data DATA1<1:8>, DATA2<1:8>, DATA3<1:8>, . . . , DATA15<1:8>, and DATA16<1:8> are inputted/outputted through the respective 16 data I/O pads DQ<1:16>. That is, the number of local lines and global lines that are necessary for the 16-bit pre-fetch scheme is two times greater than the number of local lines and global lines that are necessary for the 8-bit pre-fetch scheme. Accordingly, when the 16-bit pre-fetch scheme is applied to a semiconductor memory device using the 8-bit pre-fetch scheme, the number of data lines within the semiconductor memory device is increased two times. As a result, there are concerns that the net die of the semiconductor memory device is reduced and current consumption is increased due to an increase in the number of parallel bits to be processed at the same time.